• Design and develop embedded wafer level packaging, with emphasis on wafer level packaging process such as thin film deposition, dielectric layer process, solder bumping.
• Integrate process for embedded wafer level packaging and die embedding

Requirements:

• PhD in Mechanical Engineering or Material Science
• 3 to 5 years of industrial / research experience
• Experience in wafer level packaging, RDL & bumping, Flip-chip assembly
• Knowledge on packaging material selection, package reliability test methods
• Excellent communication skills and teamwork with strong self-motivation

Application Info:
Our Rewards
As we believe in recruiting only the best, we offer successful candidates premier remuneration package and attractive benefits plans which include Annual Wage Supplement, Performance Bonuses, Medical & Life Insurance Plans and Relocation Benefits

We invite you to apply with your full resume, including current and expected salaries, relevant experience and contact number(s).